`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/09/23 19:43:43
// Design Name: 
// Module Name: echo_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module echo_test(
    input wire        clk,
    input wire        rst,
    input wire[23:0]  switch,
    output reg[23:0]  led
    );
    
    wire rstn = ~rst;
    always@(posedge clk or negedge rstn) begin
        if (~rstn) begin
            led <= 0;
        end
        else begin
            led <= switch;
        end
    end
endmodule
